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3-19

Compiling and Elaborating Your Design

• designs with extensive use of timing such as delays, timing

checks, and SDF back annotation, particularly to

INTERCONNECT delays

• designs compiled with -debug_all

The designs that benefit the least from HSOPT are as follows:

• shallow designs — those with only a few layers of hierarchy

• designs without extensive use of timing

HSOPT is developed for Verilog and SystemVerilog code (design,

assertion, and testbench constructs) and supports the following

adjacent technologies:

• mixed HDL (VCS MX)

• OpenVera Native Testbench

• OpenVera Assertions

• AMS (analog mixed-signal)

• 64 bit compilation and simulation

• all types of coverage

• SystemC cosimulation

•Vera

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Encore SIM EDITOR SOFTWARE Guida Utente Pagina 127